Metal-oxide-semiconductor field effect transistors (FETs) generally include a substrate made of a semiconductor material, such as silicon or silicon on oxide (“SOI”). The transistors typically include a source region, a channel region and a drain region within the substrate. The channel region is located between the source and the drain regions.
A tri-gate FET is a non-planar FET which may be implemented on either a bulk silicon substrate or an SOI substrate. An SOI transistor differs from a bulk transistor in that its body is not externally biased unless a specific layout is used, such as in a body-contacted transistor. A tri-gate FET uses a raised source/drain to reduce parasitic resistances. The raised channel has an added benefit of allowing for the gate to wrap around the channel. Field effects from the wrap-around gate affect the channel on three sides, thus forming a tri-gate device. The tri-gate device allows for reducing the leakage current when the transistor is in the off state. Tri-gate devices may be fabricated as either an N-type MOS (NMOS) or a P-type MOS (PMOS). Compared to planar transistors at the same off-state leakage current, the tri-gate FET can provide higher NMOS and PMOS drive current. A pair of tri-gate FETs, one NMOS and one PMOS, can be configured together to form a CMOS device. It is desirable to provide a CMOS device having a high drive current.